The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further scaling down or micro-miniaturization of the physical dimensions of the circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, resulting in several problems.
One such problem is associated with the continuous scaling of complementary metal-oxide semiconductor (CMOS) processing requiring a borderless source/drain contact (or self-aligned S/D contact (SAC)). A conventional source/drain contact has a problem of gate-to-S/D short when the gate-to-gate pitch is further scaled. A borderless SAC prevents the gate from connecting to the S/D contact and enables a greater process window.
To realize the borderless SAC in a replacement metal gate CMOS integration scheme, one method is to form a dielectric capping layer on top of the gate to isolate the gate from the S/D contact. Theoretically, a dielectric capping layer formed to a thickness of 5 to 10 nm (depending on materials) should be good enough to isolate the S/D contact from the gate electrode. However, because of significant dielectric cap loss during the borderless contact etch, the thickness for an effective capping layer is significantly higher. For example, a capping layer of at least a thickness 20 nm is needed for enabling a SAC scheme. However, there are certain challenges associated with forming such a thick capping layer. For instance, it is challenging to form such a thick capping layer by oxidation or selective dielectric growth techniques. Further, although a metal recess followed by a dielectric capping layer deposition and polishing process is a possible approach, the higher gate height required because of the thicker dielectric capping layer results in greater burdens to the replacement metal gate fill.
A need therefore exists for methodology enabling a new contact formation scheme that reduces cap loss without increasing cap thickness, and the resulting device.